1. Technical Field of the Invention
The present invention relates generally to computer systems and, in particular, to a bus system adapted for use in a computer system having a modularized system architecture.
2. Description of Related Art
Improved system performance is a much sought-after goal of paramount significance that has been vigorously pursued in the field of computer systems since its very beginnings. Two avenues have been particularly fruitful: modularization of functional subsystems and superior bus design. Both avenues have resulted in improved system performance. In personal computers, especially, modularization has resulted in a standardized motherboard having a processor unit, on-board memory, and a host of expansion slots into which are plugged various expansion cards providing such enhanced functionality as telecommunications, disk storage and improved video.
While modularization of stand-alone computers has resulted in standard features such as those described above, the fast-growing field of network computer systems has engendered a new level of modularization altogether. It has become increasingly clear to many computer designers that having a single motherboard with a system bus thereon in a computer that is networked in a server-client relationship with other computers (known as "clients") places severe design and performance constraints on that computer (known as a "server"). Many designers of server architectures have thus adopted a design philosophy of modularizing the motherboard itself into component system boards, all of which may be plugged into system board slots provided preferably on a backplane board having interconnect circuitry. Hence, it is envisioned in such a paradigm to have a backplane board with system board slots for, for example, a processor board containing at least a processor unit, various memory modules and possibly a few expansion slots for added functionality; and at least a port board containing a host of input/output ports.
On the other hand, the goal of achieving ever-increasing performance criteria for computer systems has also mandated advanced bus design techniques. As is well-known in the art, system buses provide a communications pathway in computer systems that carries information including address information, control information, and data in accordance with a bus protocol. One problem that is common with system buses is that as the performance of a processor increases, that is, as the processing speed increases, it is necessary to provide a concomitant increase in bus transfer rate. That is, it is necessary to permit more address information, control information, and data to be transferred at faster rates on the bus so as not to nullify the advantages obtained by the use of a superior processor.
Signal propagation in a communications pathway physically occurs along an electrically conductive element, for example, a wire trace, and, as is known in the art, depends upon the frequency and length of the conductor. As operating speeds of the computer systems increase, propagation of signals between the processor and memory or peripheral devices over the communication pathway must be increasingly well controlled. For example, at relatively slow system clock and bus data rates, signal propagation characteristics remain relatively independent of the conductor length, and the signal waveform is adequately predicted and described by DC circuit analysis. At low frequencies, signals are fully absorbed (that is, non-reflected) at media discontinuities and terminal ends of the conductor, and do not affect other functional subsystems coupled to the conductor, that is, the bus.
However, as the signal frequency increases, for example, greater than around 30 MHz or so, transmission characteristics of a bus (for example, minimum cycle time, which in turn determines the maximum bus transfer rate) are no longer independent of the conductor geometry, especially the length. Two inter-related electrical parameters are of particular importance: propagation delay and settling time. The total delay associated with driving the bus includes the propagation delay through a bus driver and the period of time necessary to have the bus settle. As is known in the art, bus settling time is related, among other parameters, to the time necessary to have reflections on the bus die out before data is received by receivers on the bus.
As data rates on the system bus increases, it has therefore become necessary to minimize reflections on the bus. This is so because reflections of transmitted high frequency signals at conductor discontinuities and conductor terminations can create superimposed signals, and thereby increase the total delay and further cause unexpected results.
To preclude instances of reflected signals causing data transmission errors in high frequency data communication pathways, line terminators have been developed to match the impedance of the transmission line and thus provide a nonreflecting, that is, absorbing, termination to the transmission line. In this approach, precisely matched line terminators are coupled to terminal ends of transmission lines (that is, bus conductors) so that to the signal the lines appear to be infinite in length, causing the signal to be absorbed fully at the terminal end. Thus, by providing terminators at terminal ends of a bus interconnecting one or more subsystems, reflections on the bus are minimized or precluded altogether, thereby ensuring reliable operation of functional subsystems coupled to the bus.
Several problems are encountered in the foregoing approach to terminating the bus. One problem is that the approach does not specifically address the length-limitation of signal transmission characteristics of a high-performance bus. For example, a recently introduced high-performance system bus, known as the Peripheral Component Interconnect ("PCI") bus, that operates at least at times at 33 MHz, may not be more than about 10 inches in length. As can be appreciated, such a constraint restricts a system designer's choice as to how many devices can be loaded onto the PCI bus. It is well-known in the art that the current PCI bus architectures cannot support more than about 8-10 devices.
A second possible problem is that termination at the end of the bus requires the selection of a precisely matched impedance element although the inline component devices may vary their impedance over time. Further, termination of a bus at the ends of the bus still leaves portions of the bus between common bus conductors and individual devices on the bus unterminated. These portions can become a source of reflections on the bus as the bus frequency increases.
Another practical concern is that a system user must physically attach or detach a line terminator (hereinafter, a "terminal terminator"), to the segments of the bus depending upon certain signal transmission conditions, which conditions are often not easily ascertained by the user. For example, if no disk drive is connected at the terminal end of a Small Computer System Interface ("SCSI") bus segment, a line terminator should be attached to prevent undesirable reflections from the unterminated bus end.
More recently, switching terminators have been developed which electrically connect or disconnect a terminator circuit element from the signal pathway, without requiring physical intervention by the user. An example of such a switching terminator is the model MCCS142235, manufactured by Motorola, Inc., of Schaumberg, Ill. However, a user must still make a determination whether to engage the terminal terminator in the first instance, and then activate or deactivate the switching terminator accordingly. Further, although software interfaces could be written to enable the switching terminal terminator as necessary, the additional layer of code required on the system processor is cumbersome and would be processor-dependent.
As will be described in the following detailed description, the present invention overcomes the aforementioned problems associated with current bus designs by providing a high performance bus architecture that is geometry-independent (that is, the bus well exceeds current length specifications without compromising performance) and that has a non-terminal termination arrangement. It can be readily appreciated by those skilled in the art upon reference hereto that although a presently preferred exemplary embodiment of the present invention that is described hereinbelow involves the use of the PCI bus disposed in a server system environment, practice of the present invention is not restricted to the use of the PCI bus only, and that the present invention, whose novel features are described and claimed hereinbelow, encompasses in its scope the use of any bus standard, for example, the Industry Standard Architecture ("ISA") bus; the Extended Industry Standard Architecture ("EISA") bus; the MicroChannel.TM. Architecture ("MCA") bus or, the VL-Bus. In addition, it should be further understood that the present invention is implementable in any motherboard configuration, modularized or otherwise, disposed in any computer system.